Lead and perform advanced signal integrity simulation and analysis for high-speed interconnects, including connectors, cable assemblies, and PCB interfaces using EM and circuit simulation techniques.
Lead signal integrity design and optimization of connectors and cable assemblies to meet system-level performance requirements.
Establish signal integrity performance and functional requirements for new product development.
Review and guide PCB interface design (footprints, breakout, routing transitions) from a signal integrity perspective.
Act as the technical authority for SI-related challenges across multiple connector and cable assembly programs.
Drive technology roadmap alignment for high-speed interconnects with evolving industry requirements.
Lead customer technical discussions focused on interconnect performance, integration, and optimization.
Influence cross-functional decisions across mechanical design, materials, manufacturing, and system integration.
Drive innovation and continuous improvement in interconnect SI design, modeling, and validation approaches.
Lead and mentor engineers across regions to ensure consistency in methodologies, design quality, and technical execution.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering or a related field.
12+ years of relevant experience in signal integrity and high-speed design, including interconnect and/or system-level applications.
Deep expertise in signal integrity analysis tools (Agilent ADS, Ansys HFSS, CST, or equivalent), with extensive hands-on experience in ADS circuit simulation, channel analysis, and optimization methodologies for high-speed interconnect systems.
Strong experience with IBIS-AMI model simulation for SERDES channel performance evaluation, including advanced understanding of parameter tuning, equalization strategies, and BER/eye diagram analysis, with the ability to interpret results and guide system-level decisions.
Expert-level understanding of electromagnetic theory and electrical circuit behavior, with practical experience working with high-speed active components such as DSPs, re-timers, and re-drivers, and their interaction within system-level signal paths.
In-depth knowledge of eye diagram optimization and signal conditioning techniques, including CTLE, DFE, FFE, and emphasis settings, with the ability to analyze link margins and influence design trade-offs for performance improvement.
Proven ability to interpret and guide eye diagram and link-level performance results from an interconnect perspective, including understanding the impact of equalization techniques (e.g., CTLE, DFE, FFE) on channel behavior in collaboration with system/ASIC teams.
Demonstrated ability to define SI requirements and guide design decisions for new product development
Experience in PCB interface design considerations.
Demonstrated experience in mentoring, training, and guiding junior engineers in signal integrity and high-speed interconnect design